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Modules</h2></td></tr>
<tr class="memitem:group__xilfpga__zynq_m_p"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq_m_p.html">XilFPGA APIs for Zynq UltraScale+ MPSoC</a></td></tr>
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html">XFpgatag</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure to the XFpga instance.  <a href="struct_x_fpgatag.html#details">More...</a><br/></td></tr>
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Typedefs</h2></td></tr>
<tr class="memitem:ga2e73b67f19f7d94e00988c853ff4599b"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a></td></tr>
<tr class="memdesc:ga2e73b67f19f7d94e00988c853ff4599b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure to the XFpga instance.  <a href="#ga2e73b67f19f7d94e00988c853ff4599b">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga44b0cd1361ba0ff98ceed775997bc23b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq__versal.html#ga44b0cd1361ba0ff98ceed775997bc23b">XFpga_BitStream_Load</a> (<a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *InstancePtr, UINTPTR BitstreamImageAddr, UINTPTR KeyAddr, u32 Size, u32 Flags)</td></tr>
<tr class="memdesc:ga44b0cd1361ba0ff98ceed775997bc23b"><td class="mdescLeft">&#160;</td><td class="mdescRight">The API is used to load the bitstream file into the PL region.  <a href="#ga44b0cd1361ba0ff98ceed775997bc23b">More...</a><br/></td></tr>
<tr class="separator:ga44b0cd1361ba0ff98ceed775997bc23b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab9954493b57ad172167f25a3aa1b0eb0"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq__versal.html#gab9954493b57ad172167f25a3aa1b0eb0">XFpga_ValidateImage</a> (<a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *InstancePtr, UINTPTR BitstreamImageAddr, UINTPTR KeyAddr, u32 Size, u32 Flags)</td></tr>
<tr class="memdesc:gab9954493b57ad172167f25a3aa1b0eb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to validate the bitstream image.  <a href="#gab9954493b57ad172167f25a3aa1b0eb0">More...</a><br/></td></tr>
<tr class="separator:gab9954493b57ad172167f25a3aa1b0eb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gade4f3d3efdce2034be71f597e84a667c"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq__versal.html#gade4f3d3efdce2034be71f597e84a667c">XFpga_PL_Preconfig</a> (<a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *InstancePtr)</td></tr>
<tr class="memdesc:gade4f3d3efdce2034be71f597e84a667c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prepares the FPGA to receive configuration data.  <a href="#gade4f3d3efdce2034be71f597e84a667c">More...</a><br/></td></tr>
<tr class="separator:gade4f3d3efdce2034be71f597e84a667c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3801d1f23178289fb912ecc61cdc018d"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq__versal.html#ga3801d1f23178289fb912ecc61cdc018d">XFpga_Write_Pl</a> (<a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *InstancePtr, UINTPTR BitstreamImageAddr, UINTPTR KeyAddr, u32 Size, u32 Flags)</td></tr>
<tr class="memdesc:ga3801d1f23178289fb912ecc61cdc018d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function writes the count bytes of configuration data into the PL.  <a href="#ga3801d1f23178289fb912ecc61cdc018d">More...</a><br/></td></tr>
<tr class="separator:ga3801d1f23178289fb912ecc61cdc018d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae97b4dd15b87b8a9931a242bb855e031"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq__versal.html#gae97b4dd15b87b8a9931a242bb855e031">XFpga_PL_PostConfig</a> (<a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *InstancePtr)</td></tr>
<tr class="memdesc:gae97b4dd15b87b8a9931a242bb855e031"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the FPGA to the operating state after writing.  <a href="#gae97b4dd15b87b8a9931a242bb855e031">More...</a><br/></td></tr>
<tr class="separator:gae97b4dd15b87b8a9931a242bb855e031"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaef5fb78d2b7e74b3a4f3b18ebf0a3599"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq__versal.html#gaef5fb78d2b7e74b3a4f3b18ebf0a3599">XFpga_Initialize</a> (<a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaef5fb78d2b7e74b3a4f3b18ebf0a3599"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API, when called, initializes the XFPGA interface with default settings.  <a href="#gaef5fb78d2b7e74b3a4f3b18ebf0a3599">More...</a><br/></td></tr>
<tr class="separator:gaef5fb78d2b7e74b3a4f3b18ebf0a3599"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e98e018395a91d666b1bf5322ead85a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq__versal.html#ga5e98e018395a91d666b1bf5322ead85a">XFpga_GetPlConfigData</a> (<a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *InstancePtr, UINTPTR ReadbackAddr, u32 NumFrames)</td></tr>
<tr class="memdesc:ga5e98e018395a91d666b1bf5322ead85a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides functionality to read back the PL configuration data.  <a href="#ga5e98e018395a91d666b1bf5322ead85a">More...</a><br/></td></tr>
<tr class="separator:ga5e98e018395a91d666b1bf5322ead85a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16b3f58643bb4ca44b5f76cb15ca3c27"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq__versal.html#ga16b3f58643bb4ca44b5f76cb15ca3c27">XFpga_GetPlConfigReg</a> (<a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *InstancePtr, UINTPTR ReadbackAddr, u32 ConfigRegAddr)</td></tr>
<tr class="memdesc:ga16b3f58643bb4ca44b5f76cb15ca3c27"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides PL specific configuration register values.  <a href="#ga16b3f58643bb4ca44b5f76cb15ca3c27">More...</a><br/></td></tr>
<tr class="separator:ga16b3f58643bb4ca44b5f76cb15ca3c27"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f8e3aaa97c67aaaae6521f75f989e59"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xilfpga__zynq__versal.html#ga2f8e3aaa97c67aaaae6521f75f989e59">XFpga_InterfaceStatus</a> (<a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga2f8e3aaa97c67aaaae6521f75f989e59"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides the status of the PL programming interface.  <a href="#ga2f8e3aaa97c67aaaae6521f75f989e59">More...</a><br/></td></tr>
<tr class="separator:ga2f8e3aaa97c67aaaae6521f75f989e59"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Typedef Documentation</h2>
<a class="anchor" id="ga2e73b67f19f7d94e00988c853ff4599b"></a>
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          <td class="memname">typedef struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> <a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a></td>
        </tr>
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<p>Structure to the XFpga instance. </p>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="ga44b0cd1361ba0ff98ceed775997bc23b"></a>
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          <td class="memname">u32 XFpga_BitStream_Load </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BitstreamImageAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>KeyAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Flags</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The API is used to load the bitstream file into the PL region. </p>
<p>It supports AMD Vivadoâ„¢ Design Suite generated bitstream (*.bit, *.bin) and Bootgen-generated bitstream (*.bin) loading, Passing valid bitstream size(Size) information is mandatory for Vivado Design Suite generated bitstream, For Bootgen-generated bitstreams bitstream size is taken from the bitstream header.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the XFpga structure.</td></tr>
    <tr><td class="paramname">BitstreamImageAddr</td><td>Linear memory bitstream image base address</td></tr>
    <tr><td class="paramname">KeyAddr</td><td>AES key address which is used for decryption.</td></tr>
    <tr><td class="paramname">Size</td><td>Used to store size of bitstream image.</td></tr>
    <tr><td class="paramname">Flags</td><td>Flags are used to specify the type of bitstream file.<ul>
<li>BIT(0) - Bitstream type<ul>
<li>0 - Full bitstream</li>
<li>1 - Partial bitstream</li>
</ul>
</li>
<li>BIT(1) - Authentication using DDR<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
<li>BIT(2) - Authentication using OCM<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
<li>BIT(3) - User-key Encryption<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
<li>BIT(4) - Device-key Encryption<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XFPGA_SUCCESS on success</li>
<li>Error code on failure.</li>
<li>XFPGA_VALIDATE_ERROR.</li>
<li>XFPGA_PRE_CONFIG_ERROR.</li>
<li>XFPGA_WRITE_BITSTREAM_ERROR.</li>
<li>XFPGA_POST_CONFIG_ERROR. </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_fpga___write.html#ab3ba8d05e4395ac2f404282ac8acd2ca">XFpga_Write::BitstreamAddr</a>, <a class="el" href="struct_x_fpga___write.html#a3213fec12e94e571eadb705e21efe982">XFpga_Write::Flags</a>, <a class="el" href="struct_x_fpga___write.html#a6a67375da15c7c9b5ba870fae38bf434">XFpga_Write::KeyAddr</a>, <a class="el" href="struct_x_fpga___write.html#af17c38a1a35ad02470377430f894e403">XFpga_Write::Size</a>, <a class="el" href="struct_x_fpgatag.html#a43bcd659f5043721bf8f99df22330a19">XFpgatag::WriteInfo</a>, <a class="el" href="group__xilfpga__zynq__versal.html#gae97b4dd15b87b8a9931a242bb855e031">XFpga_PL_PostConfig()</a>, <a class="el" href="group__xilfpga__zynq__versal.html#gade4f3d3efdce2034be71f597e84a667c">XFpga_PL_Preconfig()</a>, <a class="el" href="group__xilfpga__zynq__versal.html#gab9954493b57ad172167f25a3aa1b0eb0">XFpga_ValidateImage()</a>, and <a class="el" href="group__xilfpga__zynq__versal.html#ga3801d1f23178289fb912ecc61cdc018d">XFpga_Write_Pl()</a>.</p>

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          <td class="memname">u32 XFpga_GetPlConfigData </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>ReadbackAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>NumFrames</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function provides functionality to read back the PL configuration data. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the XFpga structure</td></tr>
    <tr><td class="paramname">ReadbackAddr</td><td>Address which is used to store the PL readback data.</td></tr>
    <tr><td class="paramname">NumFrames</td><td>The number of FPGA configuration frames to read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XFPGA_SUCCESS, if successful</li>
<li>XFPGA_FAILURE, if unsuccessful</li>
<li>XFPGA_OPS_NOT_IMPLEMENTED, if implementation not exists. </li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd><ul>
<li>This API is not supported for the Versal platform. </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_fpgatag.html#acd5464c8e6c66bf80aa0139efe016bb7">XFpgatag::ReadInfo</a>, and <a class="el" href="struct_x_fpgatag.html#af817a3d9e50e29ae60448178d216df29">XFpgatag::XFpga_GetConfigData</a>.</p>

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          <td class="memname">u32 XFpga_GetPlConfigReg </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>ReadbackAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>ConfigRegAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function provides PL specific configuration register values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the XFpga structure</td></tr>
    <tr><td class="paramname">ReadbackAddr</td><td>Address which is used to store the PL Configuration register data.</td></tr>
    <tr><td class="paramname">ConfigRegAddr</td><td>Configuration register address as mentioned in the UG570.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XFPGA_SUCCESS if, successful</li>
<li>XFPGA_FAILURE if, unsuccessful</li>
<li>XFPGA_OPS_NOT_IMPLEMENTED, if implementation not exists. </li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd><ul>
<li>This API is not supported for the Versal platform. </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_fpgatag.html#acd5464c8e6c66bf80aa0139efe016bb7">XFpgatag::ReadInfo</a>, and <a class="el" href="struct_x_fpgatag.html#a112c731b7c08c57308e95856658fae97">XFpgatag::XFpga_GetConfigReg</a>.</p>

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          <td class="memname">u32 XFpga_Initialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This API, when called, initializes the XFPGA interface with default settings. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the XFpga structure.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns Status<ul>
<li>XFPGA_SUCCESS on success</li>
<li>Error code on failure </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_fpgatag.html#af817a3d9e50e29ae60448178d216df29">XFpgatag::XFpga_GetConfigData</a>, <a class="el" href="struct_x_fpgatag.html#a112c731b7c08c57308e95856658fae97">XFpgatag::XFpga_GetConfigReg</a>, <a class="el" href="struct_x_fpgatag.html#a088ada7ce0d61319dafb5bfd85290cb1">XFpgatag::XFpga_GetFeatureList</a>, <a class="el" href="struct_x_fpgatag.html#a6af355b88beaac6b872a53c13285514b">XFpgatag::XFpga_GetInterfaceStatus</a>, <a class="el" href="struct_x_fpgatag.html#a3e5baa8aaa7b73f6cd31737b2465515c">XFpgatag::XFpga_PostConfig</a>, <a class="el" href="struct_x_fpgatag.html#a542049e29b0804aabea8bcc577d71b47">XFpgatag::XFpga_PreConfig</a>, <a class="el" href="struct_x_fpgatag.html#a17d90caf2f96a1c0ce3a309015fd32ae">XFpgatag::XFpga_ValidateBitstream</a>, and <a class="el" href="struct_x_fpgatag.html#a31407cee8cfa8d58cea94bda3147e757">XFpgatag::XFpga_WriteToPl</a>.</p>

<p>Referenced by <a class="el" href="xfpga__readback__example_8c.html#a840291bc02cba5474a4cb46a9b9566fe">main()</a>.</p>

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          <td class="memname">u32 XFpga_InterfaceStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function provides the status of the PL programming interface. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the XFpga structure</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Status of the PL programming interface</dd></dl>
<dl class="section note"><dt>Note</dt><dd><ul>
<li>This API is not supported for the Versal platform. </li>
</ul>
</dd></dl>

<p>References <a class="el" href="struct_x_fpgatag.html#a6af355b88beaac6b872a53c13285514b">XFpgatag::XFpga_GetInterfaceStatus</a>.</p>

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          <td class="memname">u32 XFpga_PL_PostConfig </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function sets the FPGA to the operating state after writing. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the XFpga structure</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Codes as mentioned in <a class="el" href="xilfpga_8h.html">xilfpga.h</a> </dd></dl>

<p>References <a class="el" href="struct_x_fpgatag.html#a3e5baa8aaa7b73f6cd31737b2465515c">XFpgatag::XFpga_PostConfig</a>.</p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq__versal.html#ga44b0cd1361ba0ff98ceed775997bc23b">XFpga_BitStream_Load()</a>.</p>

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          <td class="memname">u32 XFpga_PL_Preconfig </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function prepares the FPGA to receive configuration data. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the pointer to the XFpga.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Codes as mentioned in <a class="el" href="xilfpga_8h.html">xilfpga.h</a> </dd></dl>

<p>References <a class="el" href="struct_x_fpgatag.html#a542049e29b0804aabea8bcc577d71b47">XFpgatag::XFpga_PreConfig</a>.</p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq__versal.html#ga44b0cd1361ba0ff98ceed775997bc23b">XFpga_BitStream_Load()</a>.</p>

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          <td class="memname">u32 XFpga_ValidateImage </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BitstreamImageAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>KeyAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Flags</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function is used to validate the bitstream image. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the XFpga structure</td></tr>
    <tr><td class="paramname">BitstreamImageAddr</td><td>Linear memory bitstream image base address</td></tr>
    <tr><td class="paramname">KeyAddr</td><td>Aes key address which is used for decryption.</td></tr>
    <tr><td class="paramname">Size</td><td>Used to store size of bitstream image.</td></tr>
    <tr><td class="paramname">Flags</td><td>Flags are used to specify the type of bitstream file.<ul>
<li>BIT(0) - Bitstream type<ul>
<li>0 - Full bitstream</li>
<li>1 - Partial bitstream</li>
</ul>
</li>
<li>BIT(1) - Authentication using DDR<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
<li>BIT(2) - Authentication using OCM<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
<li>BIT(3) - User-key Encryption<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
<li>BIT(4) - Device-key Encryption<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Codes as mentioned in <a class="el" href="xilfpga_8h.html">xilfpga.h</a> </dd></dl>

<p>References <a class="el" href="struct_x_fpga___write.html#ab3ba8d05e4395ac2f404282ac8acd2ca">XFpga_Write::BitstreamAddr</a>, <a class="el" href="struct_x_fpga___write.html#a3213fec12e94e571eadb705e21efe982">XFpga_Write::Flags</a>, <a class="el" href="struct_x_fpga___write.html#a6a67375da15c7c9b5ba870fae38bf434">XFpga_Write::KeyAddr</a>, <a class="el" href="struct_x_fpga___write.html#af17c38a1a35ad02470377430f894e403">XFpga_Write::Size</a>, <a class="el" href="struct_x_fpgatag.html#a43bcd659f5043721bf8f99df22330a19">XFpgatag::WriteInfo</a>, and <a class="el" href="struct_x_fpgatag.html#a17d90caf2f96a1c0ce3a309015fd32ae">XFpgatag::XFpga_ValidateBitstream</a>.</p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq__versal.html#ga44b0cd1361ba0ff98ceed775997bc23b">XFpga_BitStream_Load()</a>.</p>

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          <td class="memname">u32 XFpga_Write_Pl </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__xilfpga__zynq__versal.html#ga2e73b67f19f7d94e00988c853ff4599b">XFpga</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BitstreamImageAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>KeyAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Flags</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function writes the count bytes of configuration data into the PL. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the XFpga structure</td></tr>
    <tr><td class="paramname">BitstreamImageAddr</td><td>Linear memory bitstream image base address</td></tr>
    <tr><td class="paramname">KeyAddr</td><td>Aes key address which is used for decryption.</td></tr>
    <tr><td class="paramname">Size</td><td>Used to store size of bitstream image.</td></tr>
    <tr><td class="paramname">Flags</td><td>Flags are used to specify the type of bitstream file.<ul>
<li>BIT(0) - Bitstream type<ul>
<li>0 - Full bitstream</li>
<li>1 - Partial bitstream</li>
</ul>
</li>
<li>BIT(1) - Authentication using DDR<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
<li>BIT(2) - Authentication using OCM<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
<li>BIT(3) - User-key Encryption<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
<li>BIT(4) - Device-key Encryption<ul>
<li>1 - Enable</li>
<li>0 - Disable</li>
</ul>
</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Codes as mentioned in <a class="el" href="xilfpga_8h.html">xilfpga.h</a> </dd></dl>

<p>References <a class="el" href="struct_x_fpga___write.html#ab3ba8d05e4395ac2f404282ac8acd2ca">XFpga_Write::BitstreamAddr</a>, <a class="el" href="struct_x_fpga___write.html#a3213fec12e94e571eadb705e21efe982">XFpga_Write::Flags</a>, <a class="el" href="struct_x_fpga___write.html#a6a67375da15c7c9b5ba870fae38bf434">XFpga_Write::KeyAddr</a>, <a class="el" href="struct_x_fpga___write.html#af17c38a1a35ad02470377430f894e403">XFpga_Write::Size</a>, <a class="el" href="struct_x_fpgatag.html#a43bcd659f5043721bf8f99df22330a19">XFpgatag::WriteInfo</a>, and <a class="el" href="struct_x_fpgatag.html#a31407cee8cfa8d58cea94bda3147e757">XFpgatag::XFpga_WriteToPl</a>.</p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq__versal.html#ga44b0cd1361ba0ff98ceed775997bc23b">XFpga_BitStream_Load()</a>.</p>

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